Keynote Speakers for PACT'04

Keynote Speech #1 (Friday, October 1^st): Wen-Mei Hwu
University of Illinois at Urbana Champaign, USA

Title: Breaking Down the Memory Wall for Scalable Microprocessor Platforms (download his presentation)

Summary: Contemporary visions for scalable microprocessor computing platforms rely increasingly on decentralized models of parallelism and storage, including the use of multiple cores and hardware accelerators. This model helps to avoid the high cost of scaling individual processor cores and that of high speed interface to a monolithic, coherent memory system. The primary obstacle to the adoption of this model is that conventional compilation for imperative programs loses track of values tossed over the memory wall, preventing radical transformation of computation and data access. In particular, parallelization of C and C++ programs has been limited by the lack of safe, accurate, and scalable analyses of memory accesses in these programs. In this talk, I will present some recent breakthroughs in pointer, heap object and memory data flow analyses that will likely deliver the software transformations to empower future scalable microprocessor platforms.


Keynote Speech #2 (Saturday, October 2^nd): Tadashi Watanabe
NEC, Japan

Title: "The Earth Simulator and its Beyond - Technological Considerations towards the Sustained PetaFlops Machine -"

Summary: Since the release of early 2002, the Earth Simulator with 40 TFlops peak speed has demonstrated the fastest sustained performances in lots of applications, and brought us new findings in various application areas like the environment and nano material sciences. In this talk, the system architecture and implementation of the Earth Simulator will be introduced as well as application results and performance. Our target for the next genaration is clearly the sustatined PetaFlops machine which is a big challenge for us. There are many technological barriers to overcome that will be introduced in my talk.


Keynote Speech #3 (Sunday, October 3^rd): Stamatis Vassiliadis
T.U. Delft, The Nederlands

Title: Polymorphic Processors: How to Expose Arbitrary Hardware Functionality to Programmers (Download his presentation)

Summary: In this talk we present a polymorphic processor paradigm incorporating both general purpose and custom computing processing. This family of processors incorporates an arbitrary number of programmable units, exposes the hardware to the programmers/designers and it allows them to modify and extend the processor functionality at will. To achieve the previously stated attributes, we discuss a new programming paradigm, a new instruction set architecture, a microcode-based microarchitecture, and a compiler methodology.

The programming paradigm, in contrast with the conventional programming paradigms, allows general-purpose conventional code and hardware descriptions to coexist in a program. In the polymorphic processor paradigm, it is shown that for a given instruction set architecture an one-time instruction set extension is sufficient to implement the reconfigurable functionality of the processor.

We also discuss some microarchitectural issues and suggest that hardware emulation could allow high-speed reconfiguration and execution. We also discuss several design issues for polymorphic compilers. We also provide some evidence suggesting that the polymorphic paradigm could provide performance gains when compared to stand alone hardwired microprocessors. We also present experiments for the MPEG-2 encoder and decoder with a polymorphic processor prototype implemented in the Xilinx Virtex II Pro FPGA. We show that the overall attainable application speedup for the MPEG-2 encoder and decoder is between 2.64 - 3.18 and between 1.56 - 1.94, respectively, representing between 93% and 98% of the theoretically obtainable speedups.